1. Field of the Invention
The present invention relates to an integrated circuit, and more particularly to a power trunk line layout design method. The power trunk lines supply power to the integrated circuit at portions where logical functions of the integrated circuit are realized.
2. Description of the Related Art
In the art of integrated circuits, it has been known that a custom-oriented LSI (Large-scale Integrated Circuit), such as a sea-of-gate array and a standard cell, is effective to realize large scale, user definable, logical functions on a chip. The sea-of-gate array and the standard cell comprise one or more blocks arranged on a chip. Each block includes one or more basic cells. Each basic cell is composed of a plurality of transistors and gates.
The sea-of-gate array comprises a multiplicity of basic cells spread over the chip. The individual basic cells are arranged on no wiring areas of on the chip and has no wiring areas (channels) dedicated for wiring, thus providing a channel-free structure. On the contrary, the cell-arranged area and wiring areas (channels) of the standard cell can be designed freely.
With this prior arrangement, partly because the channels were variable and partly because the arrangement of the blocks also was variable, power trunk line design had to be done after the block layout design. Specifically, if the degree of freedom in arranging blocks was increased in attempting to realize a higher-performance logical function, the arrangement of blocks on a chip depended on the logical design and hence could not be standardized. As a consequence, the power trunk lines for supplying power also could not be standardized, and therefore the power trunk lines had to be set based on the arrangement of blocks.
FIG. 3 of the accompanying drawings shows a prior art power supply system for the above-discussed LSI.
The LSI of FIG. 3 comprises an outer logical portion 2 disposed in a peripheral area of a semiconductor chip 1, an inner logical portion 3 disposed in a central area inside the peripheral area, and a plurality of power supply points 5 preliminary and fixedly arranged along the periphery of the inner logical power 3. In the inner logical portion 3, a plurality of blocks 4 are arranged. Transisters and other elements are mounted on the blocks 4.
To supply power to the individual blocks 4, power trunk lines 9 leading from the respective power supply points 5 are arranged directly on the respective blocks 4. Power is supplied from the power supply points 5 via the individual power trunk lines 9.
Heretofore, when designing power supplies of this kind of LSI, particularly the power trunk line layout, it was difficult to retrieve the wiring course of power trunk lines. Namely, when mounting power trunk lines on the target LSI, the block layout is designed, and then lines are provided such that each line extends from a particular fixed power supply point at the periphery of the inner logical portion of one side of the chip to another fixed power supply point at the opposite side of the chip. In this case, however, the arrangement, shape and size of blocks must be considered when designing the line layout. Thus, the resulting power trunk lines would necessarily be curved or bent, as shown in FIG. 3 which makes power trunk line design complex and which requires an additional wiring area or channel so that the logical signal wiring area or channel is reduced. Consequently, logical signal wiring design is difficult.
Further, many power-trunk-line designing data are created for each LSI. The bent power trunk lines require many data designating the coordinates of the bending points as well as many wiring layers to be considered. Thus a complex power-trunk-line designing data results. With LSI, since many power trunk lines are provided, enormous designing data as a whole are required, which makes design laborious and time-consuming.
Conventional power trunk line layout in LSI did not consider either the rate of linearization of power-trunk-line wiring or wiring automation. As a consequence, the wiring course of power trunk lines could not be retrieved without difficulty. Since the resulting wiring had many bends, the rate of linearization was low. Further, since many data were required for designing of each LSI type, standardizing design algorithms, facilitating design and wiring automation could not be achieved.